1. Field of the Invention
The present invention relates to a read/write circuit for dynamic RAM devices, and particularly to a technology that is effective with direct bit bus sensing dynamic RAM devices to which the potential of a bit bus pair is input to a MOSFET gate pole to transfer data over a common data bus according to the MOSFET ON resistance resulting from the input potential.
2. Prior Art
The prior art is described below with reference to FIGS. 1 to 3.
A sense amplifier circuit is added to read data from non-addressable multiplex DRAM (c.f., Ref. 1: K. Yanagisawa, et al., 1989 ESSCIRC, pp. 184-187) and low-voltage 64 Mbit DRAM (c.f., Ref. 2: Y. Nakagome, et al., 1990 Symposium on VLSI Circuits, pp. 17-18) devices. The cross-cut flip-flop sense amplifier circuit (T9, T10, T11, and T12 in FIG. 1) is a common conventional DRAM sense amplifier circuit. In another type of sense amplifier circuit that may be used, the bit bus potential is applied to the MOSFET T1, T2 gate pole, and the ground bus (Vss) and common data buses CD and CD are connected by the ON resistance of the MOSFETs T1 and T2 and the MOSFETs T3 and T4 controlled by the column selection bus Yn selected by the column decoding circuit 5, thus enabling the data to be read and keeping the bit buses BL and BL and the common data buses CD and CD electrically separated.
These technologies were introduced because the floating capacity of the common data buses CD, CD increases as the degree of integration of the DRAM device increases, and the current drive power of the sense amplifier transistors T9, T10, T11, T12 decreases as the voltage decreases. As a result, if the bit bus and the common data bus are switch connected before the bit bus is sufficiently amplified, the data on the bit bus will be lost. This insufficient amplification of the bit bus is therefore an impediment to increasing the processing speed of the DRAM device. Bit bus direct sensing technologies were therefore introduced to electrically separate and read the bit bus and common data bus.
When the bit bus and common data bus are electrically separated as described above, however, the common data buses CD, CD cannot be used as both input and output buses, and an input data bus pair CID, CID must be provided in addition to the common data buses CD, CD. Furthermore, two MOSFETs T1 and T2 for bit bus potential sensing, and four MOSFETs T5-T8 separating the input data bus pair CID, CID and the bit bus pair BL, BL must be provided in addition to the conventional bit bus refreshing CMOS sense amplifier circuit composed of four MOSFETs T9-T12. These additional devices necessarily increase the chip size.
The bit bus pair BL, BL is not shown in FIG. 1 because it is not directly related to the present invention, but a bit bus equalizer and precharge circuit as described in Ref. 1 and Ref. 2 is, of course, connected to provide a half precharge.
The circuits shown in FIGS. 2 and 3 that are functionally identical to equivalent circuits in the preferred embodiment described below are next described.
The sense amplifier drive circuits SAD 12 are controlled by the sense amplifier activation signal, and control the sense amplifier driver. The SAD 12 also include a circuit to precharge the common source buses NS and PS of the sense amplifier circuit. The main amplifier circuits MA 13 detect and amplify the signals on the common data buses CD, CD during the read cycle of DRAM operation, and are controlled via the control bus RMA. The main amplifier circuits MA are not activated during the write cycle. The outputs of the write circuit WCKT 9 are connected to the input data bus pair CID, CID provided separately to the common data buses. The write timing signal WG 10.sup.- is generated according to the external write enable signal /WE and the column control bus. Switch control buses TGn 7 are also provided for separating the sense amplifier circuits.
When the bit bus pair BL, BL and common data bus are thus electrically separated, however, the common data buses cannot be used as both input and output buses, and a common input data bus pair CID, CID must be provided in addition to the common data buses CD, CD. Furthermore, two MOSFETs T1 and T2 for bit bus potential sensing, and four MOSFETs T5-T8 separating the input data bus pair CID, CID and the bit bus pair BL, BL must be provided in addition to the conventional bit bus refreshing CMOS sense amplifier circuit composed of four MOSFETs T9-T12. These additional devices necessarily increase the chip size.